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integrated circuit systems, inc. ics952606 0717f?06/10/05 pin configuration recommended application: ck409 48-pin part output features: 2 - 0.7v current-mode differential cpu pairs 1 - 0.7v current-mode differential cpu pairs for itp 1 - 0.7v current-mode differential src pair 9 - pci (33mhz) 1 - usb, 48mhz 1 - dot, 48mhz 2 - ref, 14.318mhz 3 - 3v66, 66.66mhz 1 - 3v66/vch, selectable 48mhz or 66mhz key specifications: cpu/src outputs cycle-cycle jitter < 125ps 3v66 outputs cycle-cycle jitter < 250ps pci outputs cycle-cycle jitter < 250ps cpu outputs skew: < 100ps +/- 300ppm frequency accuracy on cpu & src clocks programmable timing control hub? for next gen p 4 ? processor functionality features/benefits: supports tight ppm accuracy clocks for serial-ata supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread supports cpu clks up to 400mhz in test mode uses external 14.318mhz crystal supports undriven differential cpu, src pair in pd# for power management. 48-pin ssop fs2 b6b5 fs_a fs_b cpu mhz src mhz 3v66 mhz pci mhz ref mhz u sb/ dot mhz 0 0 100.00 100/200 66.66 33.33 14.318 48.00 0 1 200.00 100/200 66.66 33.33 14.318 48.00 1 0 133.33 100/200 66.66 33.33 14.318 48.00 1 1 166.66 100/200 66.66 33.33 14.318 48.00 0 0 200.00 100/200 66.66 33.33 14.318 48.00 0 1 400.00 100/200 66.66 33.33 14.318 48.00 1 0 266.66 100/200 66.66 33.33 14.318 48.00 1 1 333.33 100/200 66.66 33.33 14.318 48.00 0 1 *fsa/ref0 1 48 vdda *fsb/ref1 2 47 gnd vddref 3 46 iref x1 4 45 cpuclkt_itp x2 5 44 cpuclkc_itp gnd 6 43 gnd pciclk_f0 7 42 cpuclkt1 pciclk_f1 8 41 cpuclkc1 pciclk_f2 9 40 vddcpu vddpci 10 39 cpuclkt0 gnd 11 38 cpuclkc0 pciclk0 12 37 gnd pciclk1 13 36 srcclkt pciclk2 14 35 srcclkc pciclk3 15 34 vdd vddpci 16 33 vtt_pwrgd# gnd 17 32 sdata pciclk4 18 31 sclk pciclk5 19 30 3v66_0 pd# 20 29 3v66_1 48mhz_dot 21 28 gnd 48mhz_usb 22 27 vdd3v66 gnd 23 26 3v66_2 vdd48 24 25 3v66_3/vch **120kw pull-down ics952606
2 integrated circuit systems, inc. ics952606 0717f?06/10/05 pin description pin # pin name pin type description 1 *fsa/ref0 i/o fre q uenc y select latch in p ut p in / 14.318 mhz reference clock. 2 *fsb/ref1 i/o fre q uenc y select latch in p ut p in / 14.318 mhz reference clock. 3 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 4x1 in cr y stal in p ut, nominall y 14.318mhz. 5 x2 out cr y stal out p ut, nominall y 14.318mhz 6 gnd pwr ground p in. 7 pciclk_f0 out free runnin g pci clock not affected b y pci_stop# . 8 pciclk_f1 out free runnin g pci clock not affected b y pci_stop# . 9 pciclk_f2 out free runnin g pci clock not affected b y pci_stop# . 10 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 11 gnd pwr ground p in. 12 pciclk0 out pci clock out p ut. 13 pciclk1 out pci clock out p ut. 14 pciclk2 out pci clock out p ut. 15 pciclk3 out pci clock out p ut. 16 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 17 gnd pwr ground p in. 18 pciclk4 out pci clock out p ut. 19 pciclk5 out pci clock out p ut. 20 pd# in asynchronous active low input pi n, with 120kohm internal pull-up resistor, used to power down the device. the internal clocks are disabled and the vco and the cr y stal are sto pp ed. 21 48mhz_dot out 48mhz clock out p ut. 22 48mhz_usb out 48mhz clock out p ut. 23 gnd pwr ground p in. 24 vdd48 pwr power pin for the 48mhz output.3.3v
3 integrated circuit systems, inc. ics952606 0717f?06/10/05 pin description (continued) pin # pin name pin type description 30 3v66_0 out 3.3v 66.66mhz clock out p ut 25 3v66_3/vch out 3.3v 66.66mhz clock out p ut / 48mhz vch clock out p ut. 26 3v66_2 out 3.3v 66.66mhz clock out p ut 27 vdd3v66 pwr power p in for the 3.3v 66mhz clocks. 28 gnd pwr ground p in. 29 3v66_1 out 3.3v 66.66mhz clock out p ut 30 3v66_0 out 3.3v 66.66mhz clock out p ut 31 sclk in clock p in of smbus circuitr y , 5v tolerant. 32 sdata i/o data p in for smbus circuitr y , 5v tolerant. 33 vtt_pwrgd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active low in p ut. 34 vdd pwr power su pp l y , nominal 3.3v 35 srcclkc out complement clock of differential pair for s-ata support. +/- 300 pp m accurac y re q uired. 36 srcclkt out true clock of differential pair for s-ata support. +/- 300 pp m accurac y re q uired. 37 gnd pwr ground p in. 38 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external re sistors are required for voltage bias. 39 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 40 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 41 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external re sistors are required for voltage bias. 42 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 43 gnd pwr ground p in. 44 cpuclkc_itp out complementary clock of differential pair cpu outputs. these are current mode outputs. external re sistors are required for voltage bias. 45 cpuclkt_itp out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 46 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appr opriate current. 475 ohms is the standard value. 47 gnd pwr ground p in. 48 vdda pwr 3.3v power for the pll core.
4 integrated circuit systems, inc. ics952606 0717f?06/10/05 ics952606 is a 48 pin clock chip following intel ck409 yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ics952606 is driven with a 14.318mhz crystal. it generates cpu outputs up to 200mhz. it also provides a tight ppm accuracy output for serial ata support. general description block diagram power groups vdd gnd 3 6 xtal, ref 27 28 3v66 [0:3] 10,16 11,17 pciclk outputs 34 37 srcclk outputs 48 47 master clock, cpu analog 24 23 48mhz, fix digital, fix analog -- 47 iref 40 43 cpuclk clocks description pin number i ref pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz, usb, dot, vch x1 x2 xtal sdata sclk v ttpwrgd# pd# fs_a fs_b control logic ref (1:0) cpuclkt (1:0) cpuclkc (1:0) srcclkt0 srcclkc0 3v66(3:0) pciclk_f (2:0) cpuclkt_itp cpuclkc_itp pciclk (5:0)
5 integrated circuit systems, inc. ics952606 0717f?06/10/05 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage -0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot i nput esd protect i on human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ua i il1 v in = 0 v; inputs with no pull-up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3.3op full active, c l = full load; 260.000 350 ma all diff p airs driven 31.000 35 ma all differential p airs tri-stated 0.300 12 ma in p ut fre q uenc y 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from vdd power-up or de- assertion of pd# to 1st clock. 1.8 ms 1,2 modulation fre q uenc y trian g ular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 see timin g dia g rams for timin g re q uirements. i dd3.3pd 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet pp m fre q uenc y accurac y on pll out p uts. input capacitance 1 input low current powerdown current
6 integrated circuit systems, inc. ics952606 0717f?06/10/05 electrical characteristics - cpu & src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 749 850 1 voltage low vlow -150 3 150 1 max volta g e vovs 756 1150 1 min volta g e vuds -300 -7 1 crossin g volta g e ( abs ) vcross ( abs ) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 200mhz nominal 4.9985 5.000 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.000 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.500 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.000 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 200mhz nominal 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 279 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 280 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 50.9 55 % 1 skew t sk3 v t = 50% 8100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 40 125 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. src clock out p uts run at onl y 100mhz or 200mhz, s p ecs for 133.33 and 166.66 do not a pp l y to src clock p air. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz tperiod average period absolute min period t absmin statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
7 integrated circuit systems, inc. ics952606 0717f?06/10/05 electrical characteristics - 3v66 mode: 3v66 [3:0] t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 66.66mhz out p ut nominal 14.9955 15 15.0045 ns 2 66.66mhz out p ut s p read 14.9955 15.0799 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.79 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.69 2 ns 1 duty cycle d t1 v t = 1.5 v 45 49.9 55 % 1 skew t sk1 v t = 1.5 v 80 250 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 172 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. clock period t period 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 33.33mhz out p ut nominal 29.9910 30 30.0090 ns 2 33.33mhz out p ut s p read 29.9910 30.1598 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol@min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.79 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.69 2 ns 1 duty cycle d t1 v t = 1.5 v 45 51.2 55 % 1 skew t sk1 v t = 1.5 v 59 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 140 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. clock period t period 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol
8 integrated circuit systems, inc. ics952606 0717f?06/10/05 parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -200 200 ppm 1,2 clock period t p eriod 48.008 mhz output nominal 20.8257 20.8340 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 2 4 v/ns 1 edge rate falling edge rate 2 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.87 1 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.89 1 ns 1 duty cycle d t1 v t = 1.5 v 45 52.3 55 % 1 long term jitter 125us period jitter (8khz frequency modulation amplitude) 0.64 2 ns 1 1 guaranteed by design, not 100% tested in production. t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 5-10 pf (unless otherwise specified) electrical characteristics - 48mhz dot clock 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol
9 integrated circuit systems, inc. ics952606 0717f?06/10/05 electrical characteristics - vch, 48mhz, 48mhz, usb t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -200 200 ppm 1,2 clock period t p eriod 48.008 mhz output nominal 20.8257 20.8340 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.45 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.37 2 ns 1 duty cycle d t1 v t = 1.5 v 45 52.5 55 % 1 long term jitter 125us period jitter (8khz frequency modulation amplitude) 0.63 6 ns 1 1 guaranteed by design, not 100% tested in production. output low current i ol 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref out p ut is at 14.31818mhz output high current i oh
10 integrated circuit systems, inc. ics952606 0717f?06/10/05 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -300 300 pp m1 clock period t p eriod 14.31818 mhz output nominal 69.8270 69.8550 ns output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 11.932 ns 1 fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 11.922 ns 1 skew t sk1 1 v t = 1.5 v 14 500 ps 1 duty cycle d t1 1 v t = 1.5 v 45 53.8 55 % 1 jitter t j c y c-c y c 1 v t = 1.5 v 400 1000 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. group to group skews at common transition edges group symbol conditions min typ max units 3v66 to pci s 3v66-pci 3v66 (3:0) leads 33mhz pci 1.50 2 3.50 ns dot-usb s dot_usb 180 degrees out of phase 0.00 1.00 ns dot-vch s dot_vch in phase 0.00 1.00 ns
11 integrated circuit systems, inc. ics952606 0717f?06/10/05 general i 2 c serial interface information for the ics952606 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
12 integrated circuit systems, inc. ics952606 0717f?06/10/05 i 2 c table: read-back register pin # name control function t yp e0 1pwd bit 7 reserved reserved - x bit 6 -x bit 5 -x bit 4 rx bit 3 rx bit 2 rx bit 1 fsb freq select 1 read back rx bit 0 fsa freq select 0 read back rx i 2 c table: spreading and device behavior control register pin # name control function t yp e0 1pwd bit 7 src/src# src f ree- r unn i ng control rw free-run stoppab le 0 bit 6 src out p ut control rw disable enable 1 bit 5 rx bit 4 rx bit 3 rx bit 2 rx bit 1 cput1/cpuc1 out p ut control rw disable enable 1 bit 0 cput0/cpuc0 output control rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 src_pd# drive mode 0: driven in pd# rw driven hi-z 0 bit 6 src_stop# drive mode 0: driven in pci_stop# (byte3bit7) rw driven hi-z 0 bit 5 reserved reserved - x bit 4 cput1_pd# drive mode rw driven hi-z 0 bit 3 cput0_pd# drive mode rw driven hi-z 0 bit 2 reserved reserved - x bit 1 reserved reserved - x bit 0 reserved reserved - x i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 pci_stop# pci_stop# control 0:all stoppable pci are sto pp ed rw enable disable 1 bit 6 reserved reserved - x bit 5 pciclk5 out p ut control rw disable enable 1 bit 4 pciclk4 out p ut control rw disable enable 1 bit 3 pciclk3 out p ut control rw disable enable 1 bit 2 pciclk2 out p ut control rw disable enable 1 bit 1 pciclk1 out p ut control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 reserved reserved reserved reserved reserved reserved reserved reserved 0:driven in pd# 1: tri-stated byte 3 byte 0 - - - reserved - - reserved reserved byte 1 - reserved reserved reserved - - reserved readback of cpu(2:0) frequency byte 2 reserved reserved reserved reserved reserved reserved reserved reserved reserved
13 integrated circuit systems, inc. ics952606 0717f?06/10/05 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 48mhz_usb 2x output drive 0=2x drive rw 2x drive normal 1 bit 6 48mhz_usb out p ut control rw disable enable 1 bit 5 reserved reserved - x bit 4 reserved reserved - x bit 3 reserved reserved - x bit 2 pciclkf2 out p ut control rw sto pp able free-run 1 bit 1 pciclkf1 out p ut control rw sto pp able free-run 1 bit 0 pciclkf0 output control rw stoppable free-run 1 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 dot_48mhz out p ut control rw disable enable 1 bit 6 cpu_t/c_itp out p ut control rw disable enable 1 bit 5 3v66_3/vhc select output select rw 3v66 vch 0 bit 4 3v66_3/vhc output control rw disable enable 1 bit 3 reserved reserved - x bit 2 3v66_2 out p ut control rw disable enable 1 bit 1 3v66_1 out p ut control rw disable enable 1 bit 0 3v66_0 output control rw disable enable 1 i 2 c table: output control and fix frequecy register pin # name control function t yp e0 1pwd bit 7 test clock mode test clock mode - disable enable 0 bit 6 reserved - - - - 0 bit 5 cpu *2 test clock fs_a and fs_b o p eration - normal test mode 0 bit 4 src frequency select src frequency select - 100mhz 200mhz 0 bit 3 s p read s p ectrum t yp e down/center - down center 0 bit 2 spread spectrum mode spread spectrum enable spread off spread on 0 bit 1 ref1 out p ut control rw disable enable 1 bit 0 ref0 output control rw disable enable 1 i 2 c table: vendor & revision id register pin # name control function t yp e0 1pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 reserved reserved reserved vendor id - byte 7 - revision id - - - - - - byte 6 byte 4 byte 5 reserved
14 integrated circuit systems, inc. ics952606 0717f?06/10/05 i 2 c table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 0 bit 1 bc1 rw - - 0 bit 0 bc0 rw - - 0 i 2 c table: reserved pin # name control function t yp e0 1pwd bit 7 reserved reserved - x bit 6 reserved reserved - x bit 5 reserved reserved - x bit 4 reserved reserved - x bit 3 reserved reserved - x bit 2 reserved reserved - x bit 1 reserved reserved - x bit 0 reserved reserved - x i 2 c table: reserved pin # name control function t yp e0 1pwd bit 7 m/n p ro g enable m/n p ro g enable - disable enable 0 bit 6 reserved reserved - x bit 5 reserved reserved - x bit 4 reserved reserved - x bit 3 reserved reserved - x bit 2 reserved reserved - x bit 1 reserved reserved - x bit 0 reserved reserved - x i 2 c table: vco fre q uenc y control re g ister pin # name control function t yp e0 1pwd bit 7 n div8 n divider bit 8 rw - - x bit 6 m div6 rw - - x bit 5 m div5 rw - - x bit 4 m div4 rw - - x bit 3 m div3 rw - - x bit 2 m div2 rw - - x bit 1 m div1 rw - - x bit 0 m div0 rw - - x reserved byte 10 - - reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - reserved reserved reserved reserved reserved reserved reserved the decimal representation of m div (6:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. - - - - - - - - - - - - byte 8 - byte 11 - - - - - byte 9 - writing to this register will configure how many bytes will be read back, default is 08 = 8 bytes.
15 integrated circuit systems, inc. ics952606 0717f?06/10/05 i 2 c table: vco frequency control register pin # name control function t yp e0 1pwd bit 7 n div7 rw - - x bit 6 n div6 rw - - x bit 5 n div5 rw - - x bit 4 n div4 rw - - x bit 3 n div3 rw - - x bit 2 n div2 rw - - x bit 1 n div1 rw - - x bit 0 n div0 rw - - x i 2 c table: spread spectrum control register pin # name control function t yp e0 1pwd bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x i 2 c table: spread spectrum control register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 ssp13 rw - - x bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x - byte 14 - - - - - - - it is recommended to use ics spread % table for spread programming. these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread programming. byte 13 - - - - - - - - byte 12 - the decimal representation of n div (8:0) is equal to vco divider value. default at power up = latch-in or byte 0 rom table. - - - - - - -
16 integrated circuit systems, inc. ics952606 0717f?06/10/05 pd# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. when pd# is asserted low all clocks will be driven low before turning off the vco. in pd# de-assertion all clocks will start without glitches. pd#, power down # n w d r w pu p c# u p cc r s# c r s6 6 v 3i c p / f i c pt o d / b s uf e re t o n 1l a m r o nl a m r o nl a m r o nl a m r o nz h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1 0r o 2 * f e r i t a o l f t a o l f2 * f e r i t a o l f r o t a o l fw o lw o lw o lw o l notes: 1. refer to tristate control of cpu and src clocks in section 7.7 for tristate timing and operation. 2. refer to control registers in section 16 for cpu_stop, src_stop and pwrdwn smbus tristate control addresses. pd# should be sampled low by 2 consecutive cpu# rising edges before stopping clocks. all single ended clocks will be held low on their next high to low transition. all differential clocks will be held high on the next high to low transition of the complimentary clock. if the control registe r determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. when the drive mode but corresponding to the cpu or src clock of interest is set to '0' the true clock will be driven high at 2 x iref and the complementary clock will be tristated. if the control register is programmed to '1' both clocks will the tristated. pwrdwn# cpu, 133mhz cpu#, 133mhz src, 100mhz src#, 100mhz 3v66, 66mhz usb, 48mhz pci, 33mhz ref, 14.31818 pd# assertion
17 integrated circuit systems, inc. ics952606 0717f?06/10/05 the time from the de-assertion of pd# or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mode control bit for pd# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mv in less than 300 s of pd# deassertion. pwrdwn# tstable <1.8ms tdrive_pwrdwn# <300 s, >200mv cpu, 133mhz cpu#, 133mhz src, 100mhz src# 100mhz 3v66, 66mhz usb, 48mhz pci, 33mhz ref, 14.31818 pd# de-assertion the 3v66_4/vch pin can be configured to be a 66.66mhz modulated output or a non-spread 48mhz output. the default is 3v66 clock. the switching is controlled by byte 5 bit 5. if it is set to '1' this pin will output the 48mhz vch clock. the outp ut will go low on the falling edge of 3v66 for a minimum of 7.49ns. then the output will transition to 48mhz on the next rising edge of dot_48 clock. 3v66 3v66_4/vch dot_48 7.4 9 ns min 3v66_3/vch pin functionality
18 integrated circuit systems, inc. ics952606 0717f?06/10/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
19 integrated circuit systems, inc. ics952606 0717f?06/10/05 index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) ordering information ics952606 y flft example: designation for tape and reel packaging rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y f lf t
20 integrated circuit systems, inc. ics952606 0717f?06/10/05 revision history rev. issue date description page # e 6/9/2005 1. updated pinout and pin description. 2. updated lf orderin g information to rohs compliant. 1-3, 19 f 6/10/2005 updated block diagram 4

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